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f3 pwm controller ice3bs03ljg off-line smps current mode controller with integrated 500v startup cell ( latched and frequency jitter mode ) never st op t h inking. power management & supply version 2.0, 6 dec 2007 http://
ed ition 20 07-12 -6 pu blis hed b y infineo n tec hno lo gies ag, 8 1726 m unich , germany , ? 2 007 infineo n tech no lo gies ag. all ri ghts reser v ed. l e ga l disclaimer t he informatio n give n in this d o cu ment sha l l in no ev ent be rega rd ed as a g uaran te e of c ond itions o r c harac te ris t ic s. with re spe c t to an y ex ample s or h i n t s give n herein, any typ i cal va lu es s t a t e d herein an d/or a n y information re garding th e a pplication of th e d e vice , in fine on t e c hno lo gies her eb y dis c laims any an d all wa rran ties a nd liab ilities of an y k i nd, inc l uding wi thou t lim i t a tion , warranties of no n-infrin g e men t of intellec t ua l prop erty right s o f any th ird p a rty . informati o n for further information on technology, delivery terms an d conditions and prices, please contact your nearest infineon technologies office (www.infineon.com ). warnings du e to tec hnic a l req u iremen t s , c o mp onen t s may c ont a i n d ang erous s u b s t a n c es . fo r information on the typ e s in q ues tion , plea se c ont ac t y our nea re st infineo n t e c hno logies o f fice. infineon technologies components may be used in life-s upport devices or systems onl y with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. f o r que stions on tech nolog y, de liv e ry and prices ple a se co ntact the infin eon te chn o logies offic e s in ge rm any or the infineon t e c hnolo g ies co mpan ies an d r epres entat ive s worldwide : se e our web page a t http:// ww w.in fine on.co m f3 p w m c o nt ro ll er ice3bs03ljg re vision history: 2007 -1 2-6 d a tash eet prev ious ve rsion: 1.0 pa ge sub j ects (major cha nge s sinc e last re vision )
type marking package f osc ice3bs03ljg 3BS3LJ pg-dso-8 65khz version 2.0 3 6 dec 200 7 f3 pwm controller ice3bs03ljg c vcc c bulk co nv e r t e r dc o u t p ut + ice 3 bs 03 lj ( lat ch & ji t t er ) snubber power management pwm controller current mode 85 -- 270 vac typical application r sense gate cs startup cell hv precise low tolerance peak current limitation fb vcc control unit - active burst mode auto restart mode latch off mode gnd bl off-line smps current mode cont roller wit h integrated 500v startu p cel l ( lat c he d a n d frequency jitter mode ) p-dso-8-3, - 6 pg -dso-8 descript i on the ice 3 bs0 3lj g is the lates t ve rs ion of the f 3 con t roller fo r lowe st s t a ndb y powe r an d low emi fe atures with b o th auto-res t a r t and latch off protec tion fea t u r e s to enh anc e th e s y s t e m robu stnes s. it ta rg ets for o f f-line batte ry ada pters, a nd lo w c o st s m ps fo r lo w to mediu m po wer r a n g e su c h as ap p lic at io n fo r th e d v d r/ w, dv d co m b i, blue ray d v d playe r an d rec o rder, s e t top bo x, c harge r, note boo k adap te r, e t c . th e inh e rited ou ts tandin g fea t ures includ es 500 v startup c e ll, a c tive b u rst mod e (ach ieve th e lowes t s t a ndb y pow er; i.e . <100 mv at n o lo ad with vin=270 vac ) an d p r o pag atio n delay c o mpe n s a tio n (a cc urate o u tput powe r lim i t for wide ra nge inp u t), mod u lated g a te drive (low emi), etc. t he n e wly a dde d te ch nolog y a nd fe atures ca n fu rther e nhan ce the fe atures. it in clud es bicmos tech nol og y (further low e r po wer co nsu m ption an d ex te nd vc c op erating rang e to 26v ), freq uen cy jittering feature (l o w emi), built-in so ft start, built-in b l a n kin g windo w with e x tend able b l a n kin g time for high load jump , ex te rn al latch o f f e nab le p i n (feas ib le for ex tra p r o t e c tio n ), e t c . t herefore, ice3b s 03 ljg is a versatile pwm controller for low to medium power application. product highlights ? ac t ive b u rs t mo de to rea c h the lowe st stan dby p o wer requirements < 100mw ? b u i lt-in latche d off pr otection mo de an d external la tc h ena b le fun c tio n to inc r ea se robu stnes s of the s ystem ? b u i lt-in an d exten dab l e b l a n king wind ow for high loa d ju mps to inc r ea se sy stem reliability ? f req u en cy jitter for low em i ? p b - free lead p l a t ing ; roh s comp ilan t features ? 500 v sta r tup c e ll s w itched o f f afte r start up ? a ctive bu rst mo de for low e st stand by pow e r ? f as t loa d ju mp resp ons e in a c tive burs t mod e ? 65k hz interna l ly fixe d s w itching frequ enc y ? b uilt-in la tc hed off p r o t e c tio n mod e for ove r temp erature, ov ervo ltag e & short win d ing ? auto res t art protection mod e fo r ove r lo ad, o pen l o o p & v c c un de rvol ta ge ? b ui l t -i n so ft sta r t ? b u ilt- i n bl an k i ng w i n d o w with exten dab le blank ing time for sho r t duration hig h c u rrent ? e xterna l latch o f f ena ble fu nction ? m ax d u ty cyc l e 75% ? o ve ra ll toleranc e of c u rre n t l i miting <
f3 pwm controller ice3bs03ljg table of contents page version 2.0 4 6 dec 200 7 1 pin configurati on and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1. 1 p i n conf igurati o n w i t h pg-dso-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 p in functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 r epresentat ive blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 f unctional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 i ntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 p ower management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 i mproved current mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3.1 p wm-op . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.3.2 p wm-comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.4 s tartup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 3.5 pwm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3.5.1 o scillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3.5.2 p wm-latch ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3.5.3 g ate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3.6 c urrent limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3.6.1 l eading edge b l anking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 3.6.2 p ropagation delay com pensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 3.7 c ontrol unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3.7.1 b asic and extendable blankin g mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3.7.2 active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3. 7. 2. 1 e ntering active burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 3.7.2.2 w orking in active burst m ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 3. 7. 2. 3 leavi ng acti ve burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 3.7.3 p rotection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 3.7.3.1 latched off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 3. 7. 3. 2 a uto r e start mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 4 e lectrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4. 1 a bsol ute maxi mum rati ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4.2 o perating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4.3 c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4.3.1 s upply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4.3.2 i nternal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 4.3.3 p wm section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4. 3. 4 s of t st art time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 4.3.5 c ontrol unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 4.3.6 c urrent limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 4.3.7 d river section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 5 o utline dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 6 m arking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
version 2.0 5 6 dec 2007 f3 pwm controller ice3bs03ljg pin configurati on and functionality 1 p in configuration and functionality 1.1 pin configuration with pg-dso-8 figu re 1 pin configuration pg -ds o -8 (top v i ew) 1.2 p in functionality bl (e xtend e d blan king an d latch o f f ena b le) the bl pin co mbine s th e fun c tions of exten dab le blank ing time for en te rin g the au to re start protec tion mode an d the ex te rn al latch off en able. t he exten dab le blank ing time func tio n is to ex tend the built-in 2 0 ms blank ing time by add in g an ex te rn al c apa ci to r at bl to ground . th e e x terna l latch off en able func tion is an ext e r n a l a cce ss to la tc h of f the ic . i t i s tr i gge re d by pulling dow n th e bl pin to le ss than 0 . 2 5 v. fb (f eed bac k ) the information ab out th e re gulation is prov id ed by the fb pin to the internal protec tion un it and to th e in te rn al pwm-comp arator to co ntro l the d u ty cy cle. the f b - signal is the only co ntrol in ca se of light loa d at the active bu rst mod e . cs (c urr e n t se nse) the c u rre n t s ens e pin se ns es the v o lta ge d e ve lo ped on the s e ries res i stor inse rted in th e so urce o f the powe r mosf e t. if cs reac hes the internal th re sho l d of the c u rre n t l i m i t comp arator, the drive r ou tp ut is imm ediately switche d off. furthermore, this c u rre n t in fo rmat io n ca n be u s ed to re alize the c u rren t mode operation throu gh the pwm-comp arator w here it comp ares with fb sig nal. gate the gate pin is the ou tp ut of th e interna l driver stage con nec te d to the ga te o f an ex ternal powe r mos f et. hv (h ig h vol t a g e) the high voltage pin is co nne cted to th e rec t ifie d dc in put vo lta ge. it is th e inp u t fo r the integrated 500v s t ar tu p ce ll. vcc (powe r sup p ly) the vcc pin is the po sitiv e sup p ly of the ic . the operating ran ge is betwe en 10.5v a nd 26v . gnd (g rou nd) t h e g n d pi n is th e gr ou n d of t h e c o n t r o l l e r . pin s ymbo l f u n ction 1 bl e x t ende d blank ing an d latch o f f en able 2 f b f e edb ack 3 c s c ur re nt s e n s e 4 g ate g a t e drive r ou tp ut 5 h v h igh v o lt age input 6 n .c . no t co nnec ted 7 v cc co ntro lle r sup p ly v o lt ag e 8 g nd co ntro lle r groun d packag e pg -dso-8 1 6 7 8 4 3 2 5 gnd bl fb cs vcc n. c. gate hv
version 2.0 6 6 dec 2007 f3 pwm contr o lle r ice3bs03ljg representative blockdiagram internal bias voltage reference oscillator duty cycle max x3.2 current limiting pwm op current mode soft start c2 25.5v r fb power management c bk c vcc 85 ... 270 vac c bulk + converter dc output v out pwm comparator c3 4.0v c4 4.0v gate driver 0.72 clock r sense 10k ? d1 c6a 3.0v c5 1.23v c10 r s q auto restart mode & g7 & g5 & g9 1 g8 0.9v s1 1 power-down reset cs bl gnd c7 c8 fb pwm section control unit ff1 c12 & 0.25v leading edge blanking 220ns 25k ? 2pf 5.0v g10 1pf propagation-delay compensation 5.0v undervoltage lockout v csth g2 - ice3xs03lj-f3 pwm controller ( latch and jitter mode ) snubber vcc startup cell c6b & g6 3.5v & g11 active burst mode 0.6v 10.5v 18v #1 # : optional external components; #1 : c bk is used to extend the blanking time #2 : t ae is used to enable the external latch off feature freq. jitter 20ms blanking time 20ms blanking time 120us blanking time soft start block soft-start comparator spike blanking 30us t2 3.25k ? 5.0v t1 t3 0.6v i bk vcc latch off enable signal t ae c9 0.25v #2 c11 1.66v spike blanking 190ns latched off mode reset v vcc < 6.23v spike blanking 30us g3 latch off mode thermal shutdown t j >130c 1 hv gate 1 ms counter 2 r epresentative blockdiagram fi gu re 2 r e p r e s e nt at ive b l o c kd ia gr am
version 2.0 7 6 dec 2007 f3 pwm controller ice3bs03ljg functional description 3 functional description all va lu es whic h a r e us ed in the func tion al d e sc rip t ion are typ i c a l v a lue s . fo r ca lc ulating th e w o rst c a se s the min / m a x va lu es whic h c an be fo und in sec t io n 4 electric al cha r a c teris t ic s hav e to be co nside r e d . 3.1 i ntroduction ice 3 bs0 3lj g is an e nha nce d v e rsion of the f 3 p w m con t roller (ice3x s02 ) for the low to me dium pow er applic atio n. th e partic u lar e nha nce d fea t u r e s are the built-in features for soft s t art, blank ing wind ow and freq uenc y jitter. it a l so prov id es th e flex ibility to in creas e th e b l a nkin g win dow by simp ly a dding capa citor in bl p i n . to in crea se th e rob u stne ss and f l e x ib il ity of th e pr ot e c ti on feature, an ex ternal latch-off enab le fe ature is ad ded. mo re ov er, the p r o v en outstan ding fea t u r e s in f 3 pwm c o n t roller are s t ill re mained suc h as the active b u rst mode , prop aga tion delay com pens ation, mod u lat ed g a te drive, protec tion fo r vc c o v erv olta ge, ov er te mpe r a t u r e , o v er load , o pen lo op, etc. the in te llige n t active b u rst mod e at stand by mode can effec t iv e o b tain the lo wes t st a ndb y po wer at minimu m l o a d an d no lo a d c o nd it io ns . a f t e r en te ri ng th is bu rs t m o d e , t h er e is s t i ll a fu ll c o nt ro l of t h e po w e r co n v e r s i o n by th e s e co ndary s i d e v i a the sam e op to co upler tha t is use d for th e norma l p w m co ntro l. th e resp ons e on lo ad jum p s is optimize d . the vo ltag e ripple o n v ou t is min i mized . v ou t is on wel l cont rolled in this mode. the u s ua l e x ternally c onn ected rc-filter in the fe edba ck line a f ter th e optoc oup le r is integ r a t e d in the ic to re duc e th e externa l p a rt co unt. furthermore, a h i g h v o ltage startup cell is integrated in to the ic which is switch ed o f f o n ce the und e rvoltage loc kou t on-thresh old of 18 v is exc e e ded. the ex te rn al startu p res i s t o r is no lo nge r n ec ess ary a s this sta r tup cell can dire ctly c onne cted to the in put bu lk ca pac itor. powe r los s es are th erefore re duc ed. th is in creas es the efficie n cy u nde r light lo ad co nditions d r a s tic a lly. adop ting the bicmo s tec hno lo gy, it can furth e r dec re ase the po wer c ons ump t ion a nd prov id e a e v en bette r stand by in put po wer. besi d e s, it also in creas es t h e design flexibilit y as the vcc voltage r a nge is exten ded to 26v . the b u ilt-in so ft start time at 20ms can provide suffic i ent timing to re duc e the ov er-s tres s at pow er mosfe t and the ou tp ut rec t ifier d u rin g startu p. t h er e ar e 2 m o de s of bl an ki ng ti m e f o r hi gh lo a d ju mps ; the b a sic mo de a nd the e x tend able mo de. the blank ing time fo r th e b a sic mod e is set a t 20ms wh ile th e ex te nda ble mo de will in creas e the blan king time at bas ic mo de by add in g e x ternal c apa citor at the bl pin. during this time w i n dow the o v erload detec tion is disab l ed. with this c onc ept no further ex te rn al c o mpo nen ts are n e ce ss ary to a d just the blank ing wind ow. in o r d e r to inc r e a se th e rob u stne ss and sa fe ty of the s ystem , the ic prov ides 2 le ve ls of p r o t e c tion mo des : la tc hed off m ode and auto re start mode . t he la tc hed off mo de is only en te re d u nde r da nge ro us c ond itions wh ich ca n d a mag e the smp s if no t switch ed off immed i a t e l y . a restart of th e s ystem can only be do ne b y rec ycling th e ac line. in ad dition , for this en hanced ve rs ion, there is an ex te rn al latc h en able func tio n prov id ed to increa se the flex ib ility in protec tion . whe n th e bl pin is pu lled d o wn to less th an 0.25v , the la tc h off mod e is trigge re d. th e a u to r e start mod e red u c e s th e a v erag e p o we r c onv ersion to a minimum und er u n sa fe o perating c ond itions . this is n e ce ss ary for a prolong ed fa ult c ond ition which c ould otherwise lead to a des tru c tio n o f the s m ps ov er time . o n ce th e malfunc tio n is remo ved , no rm al o peration is au to matically retaine d afte r the n e x t s t ar t u p p h ase. th e internal prec ise p eak current co ntro l red u ce s the c o sts for the trans former and th e se con dary diode . t h e influen ce o f th e ch ang e in the in put v o lta ge o n the ma ximum po wer limitation ca n be av oide d to gethe r with the in te grated p r o pag atio n de la y co mpen sa tion . th erefore the ma ximum pow er is nea rly inde pen den t on the in put vo lta ge, wh ic h is re quired fo r wide ran g e smp s . thu s the r e is n o n eed fo r th e ov er-sizing of the smp s , e . g. th e tran sformer and the ou tp ut d i o de. fu rthe rm ore, this e nha nce d ve rs ion impleme n ts the fre que ncy jitter mo de to th e s witc h ing cloc k a n d mo dulated gate driv e s i gna l at th e ga te pin suc h tha t the emi nois e will be effec t ive l y re duc ed. 3.2 p ower management th e un dervo ltag e lo cko ut monitors the e x ternal s upp ly vo ltag e v vc c . wh en the smps is plu gged to the ma in line, the in te rn al startu p c e ll is bia s ed an d s t a r ts to c harge th e ex te rn al ca pac ito r c vcc which is c onn ected to the vcc p i n. this vcc ch arge c u rrent is c ontrolle d to 0 . 9 m a by the startup cell. wh en the v vcc ex ce eds the on -thres hold v cco n =18 v , the bias c i rc uit are switch ed o n . th en the star tu p ce ll is sw itc hed off by th e u nde rv oltage lo ck out and the r e f ore no p o we r los s es p r e s en t due to the co nne ction of the sta r tup ce ll to the drain v o ltage . t o a v oid unc ontrolled ring in g a t s w itc h -on a h ysteres is s t a r t u p v o ltage is imple m ented . th e s w itch-off of the co ntro ller can on ly tak e pla c e afte r ac tiv e mo de w a s entered and v vcc falls below 10.5v . th e max i mum c u rre n t c ons ump t ion before the c ontrolle r is ac tiv a ted is abo ut 2 5 0 a. when v vcc falls be lo w th e off-thresh old v cco ff =10.5v, the b i a s circu i t sw itc hed o f f and th e soft start c oun te r is
f3 pwm controller ice3bs03ljg functional description version 2.0 8 6 dec 200 7 res e t. thu s it is ens ured th at at ev ery startu p c y c l e the soft start st ar ts at zer o . f i g u re 3 p ow er ma nag emen t t he interna l bias circ uit is s w itc hed off if la tc hed off mo de or au to r e start mode is entered . th e cu rren t c ons umption is then red u ce d to 2 5 0 3.3 i mprove d curre nt m o de figu re 4 c urrent mode current mo de mean s the du ty c ycle is c ontrolled by th e slop e o f the primary current. th is is don e b y c o mp arin g th e fb sign al with the am plified c u rre n t s ens e sign al. figu re 5 p ulse wid t h mo dulation in c a se the amplifie d c u rrent s ens e s i gna l exc e e d s th e fb sign al, the on -time t on of the drive r is finis hed by re se tting the pwm-la tc h (s ee figu re 5 ) . the prima r y current is se nse d by the e x ternal se ries re sistor r s e ns e ins e rted in the so urce of the ex ternal p o w e r m o s fe t . b y m e an s of c u rr en t m o de re gula t ion , th e sec ond ary outpu t vo ltag e is ins ens itiv e internal bias voltage reference pow e r m a n a gem e nt latched off mode reset v vcc < 6.23v 5.0v latched off mode undervoltage lockout 18 v 10.5v power-down reset active burst mode auto restart mode startup cell vcc hv soft start block x3.2 pwm op improved current mode 0.6v c8 pwm-latch cs fb r s q q driver soft-start comparator t fb am pl i f i ed c u rre n t sig nal t on t 0.6v driver
f3 pwm controller ice3bs03ljg functional description version 2.0 9 6 dec 200 7 to the line variations . t he c u rre n t wav e form slope will c han ge w i th th e line va riati on, w h ich co ntro ls the duty cy cl e. t he ex te rn al r se nse allows an ind i v i dua l a d justme nt o f th e ma x i m u m s o ur ce cu rr en t o f th e e x te rn al po w e r mos fet. t o improve th e cu rren t mo de du rin g lig h t lo ad c ond itions the amp l ified current ramp of the pwm-op is sup e rim pos ed o n a voltage ra mp, wh ic h is built by the switch t2 , th e v olta ge sou r c e v 1 a nd a res i s t o r r1 (see figure 6). every time t h e oscillator shuts down f o r maximum duty cycle limit at ion the s w itch t 2 is clos ed by v os c . when the osc i llator tr igge rs the gate driv er, t 2 is o pened so that the vo ltag e ra mp ca n start. in ca se of lig h t loa d th e amp l ified cu rren t ramp is too s m all to ens ure a stab le re gulation . in tha t c a s e the vo ltag e ra mp is a w e ll defined signa l for the c o mpa r is on with th e f b -signa l. t he duty cyc le is th en c ontrolled by the s l o pe of th e voltage ra mp. by mean s of the time de la y circu i t whic h is trigge re d by the inv e rte d v osc sign al, the ga te driv er is switche d -off u n til it reac he s app ro ximately 1 56n s de la y time (s ee f i g u re 7). it allo ws the d u ty cy cle to be re duc ed c ontinuo usly till 0 % by dec reas in g v fb be lo w th at thres hold. f i g u re 6 i mprov ed cu rren t mod e figu re 7 l ight loa d con d ition s 3.3. 1 p wm-op the inpu t o f th e pwm-op is ap plied o v er the internal lead in g ed ge bla n king to th e ex te rn al se nse re sistor r se nse co nne cted to pin cs. r se nse co nve r ts the s ource cu rren t in to a se nse v o lta ge. t he se nse v o lta ge is amp l ified w i th a ga in of 3.2 by p w m op. th e o u tput of th e pwm-op is co nne cted to the v o lta ge sou r c e v 1 . the v o ltage ramp w i th the s upe rimpo s e d amplifie d cu rren t s i gna l is fed into th e po sitiv e inp u ts o f the pwm- comp arator c8 a nd the s o ft-start-co m pa ra to r (se e fi gu re 6 ) . 3.3.2 p wm-comparator the pwm-co mparator c o mp ares th e s ens ed current sign al of th e ex te rn al powe r m o sfet with th e fe edb ack s i gnal v fb (s ee figu re 8). v fb is created by a n ex te rn al optoc oup le r or externa l trans istor in co mbination with th e inte rnal pull -up resist or r fb an d provid es the lo ad informati on of the feed bac k circu i try. when the amplifie d c u rre n t sign al of the ex te rn al po wer mosf e t ex ce eds th e sig nal v fb th e pwm- comp arator s w itche s off the gate driver. pwm op 0.6v 10k ?
f3 pwm controller ice3bs03ljg functional description version 2.0 1 0 6 dec 200 7 fi gu re 8 p wm c o n t r o l lin g 3. 4 s tar t up ph ase fi gu re 9 s o ft st ar t in the s t a r tup phas e, the ic prov ides a so ft start period to control the maximum primary current by means of a duty cycle limita tion. the soft start function is a built-in func tio n and it is c ontrolled by a n internal co unter. figu re 1 0 s o ft start ph ase when th e v vcc ex ce eds the on-thresh old vo lta ge, th e ic s t a r t s t he so ft st ar t mod e (s ee fi gu re 1 0 ) . the fu nc tion is realize d by an interna l soft s t a r t re sistor, a n c u rrent s i nk and a c oun ter. a nd th e amp l itude of th e c u rre n t s i n k is c ontrolle d b y th e co unter (s ee figu re 1 1 ). figu re 1 1 s o ft start circu i t af te r t h e i c i s s w i t che d on , the v sf o f ts v o ltage is co ntro lled su ch th at t he v o ltage is inc r eas ed step- wise ly (32 steps ) with th e in c r e a s e of the cou n ts. th e soft start c o u n ter wou l d se nd a sign al to the current sink co ntro l in ev ery 6 00u s s u ch th at the c u rre n t sink x3.2 pwm op i m pr ove d cur r ent m ode pwm comparator cs soft-start comparator 5v c8 0.6v fb optocoupler r fb pwm-latch soft-start comparator so f t st a r t & g7 c7 gate driver 0.6v x3 . 2 pwm op cs soft s tart counter soft start soft start finish softs v softs v softs2 v softs1 5v r softs soft start counter i 2i 4i softs 8i 32i
f3 pwm controller ice3bs03ljg functional description version 2.0 1 1 6 dec 200 7 d e crea se gradu ally a nd the du ty ratio of the ga te drive in cr ea se s gr ad u a ll y. t h e s o ft s t a r t w i l l be fin i s h ed in 20 m s ( t sof t -sta rt ) after the ic is s w itc hed on . at th e e n d o f the s o ft start period, the c u rre n t sink is switch ed off. f i g u re 12 ga te d r ive s i gna l un der soft-start p has e with in th e s o f t st ar t pe ri od , the d u ty c y c l e is in crea sing from zero to max i m u m gradu ally (s ee figu re 1 2 ). figure 13 start up phase in add ition to start-up , so ft -start is a l s o ac tiv a ted at eac h restart a t temp t du ring a u to res t art. the start- up time t sta r t-up be fo re the co nve r ter o u tput vo ltag e v out is settled, mus t b e s horte r tha n the s o ft- start ph ase t soft -star t (s ee figu re 1 3 ). by means of soft- start ther e is an ef fect ive minimiza tion of c u rrent a nd vo ltag e s t res s e s on th e ex te rn al p o wer mosfe t , the cla m p circ uit a nd th e outpu t ov ersh oot and it h e lp s to prev ent saturation of th e tran sformer during start-up . 3.5 p wm sect ion f i g u r e 14 pw m se c t io n b l o c k 3.5.1 o scilla t o r the o s c i llator g ene ra te s a fixe d freq uenc y of 6 5 kh z with freq uen cy jitte r in g of 4 % (wh i ch is 2.6kh z) at a jitterin g period of 4ms . a c apa citor, a cu rren t sou r c e a nd a cu rren t sink whic h determine the fre que ncy a r e integ r a t ed . th e c h a r g i n g and disc harging current of the implem ented o s c i llator ca pac itor a r e in te rn ally trimm ed, in orde r to ach i e v e a ve ry ac cu ra te sw itc h ing freq uen cy. t he ratio of co ntro lled c harge to disc harge c u rre n t is ad ju sted to re ac h a maximu m d u ty cy cle limitation of d ma x =0. 7 5. onc e the so ft start p e rio d is ov er and when th e ic goe s into normal ope ra ting mo de, th e switch in g freq uenc y of th e cloc k is v a rie d by the c ontrol sign al from the so ft t v softs32 v s o fts gate dri v e r t t soft-start t t v s o fts t v so fts 3 2 4.0v t soft-start v out v fb v out t start-up o s c ill a t o r d u ty c y c l e ma x gate driver 0.75 clock & g9 1 g8 pwm se c t i o n ff1 r s q soft start comparator pwm comparator current limiting frequency jitter soft start block gate
f3 pwm controller ice3bs03ljg functional description version 2.0 1 2 6 dec 200 7 start b l o c k . th en th e switch in g freq uenc y is va ried in ran ge of 6 5 khz 2.6khz at pe rio d of 4m s. 3. 5 . 2 p wm -l at ch f f the out p ut of the oscillato r block provides continuous p u lse to the pw m-l a tch w h ich turns on/off the externa l p o wer mo sfet . a f ter the pwm- latch is set, it is reset b y the pwm co mparator, the soft start co mparator o r the current -limit co mparator. when it is i n reset mode, the ou tp ut o f the ga te drive r is sh ut d o wn imme diately. 3 . 5.3 g ate driver f i g u re 15 gate driver t he driv er-stage is optimized to m i n i miz e emi an d to p r o v ide high c i rc uit effic i enc y. t h is is don e by reduc ing the sw itch o n s l ope whe n exc eed in g the e x ternal p o we r mos fet th re sho l d . this is ac hiev ed b y a slope co ntro l o f th e rising ed ge at the gat e driv er?s o u tput (s ee figure 16 ). figure 16 gate rising slope thu s th e le ading s w itc h on spik e is minimiz ed. furthermo re the d r ive r c i rc uit is de sign ed to elim in ate cros s co nduc tio n of the o u tput s t age . during p o wer up , wh en vc c is be lo w th e und ervo ltag e lock out thres hold v vcco ff , the o u tput o f th e ga te driv er is se t to low in orde r to dis able p o wer tra n sfer to th e se condary sid e . 3.6 c urrent limiting figu re 1 7 c u rre n t l i m i ting bloc k the r e is a c y c l e by cy cle pea k c u rre n t limiting op eratio n re alized by th e cu rren t-li mit co mparator c 10. th e so urce cu rren t of the ex ternal p o we r mosf et is se nse d via an externa l s ens e resis t o r r s ens e . by m eans of r sen s e th e so urce c u rre n t is trans formed to a s ens e vo ltag e v s e ns e wh ich is fed into th e pin cs. if th e vo ltag e v se nse e x c eeds the internal thres hold voltage v cst h , th e co mparator c1 0 immedia t e l y tu rn s off th e ga te driv e by re se tting the pwm la tc h ff1 . a prop agation delay comp ens ation is a dde d to su pport the imme diate sh ut dow n of the e x ternal po wer mosf et with very s hort p r o pag atio n de la y. t hus th e influ enc e of the ac inpu t vo ltag e on th e max i mu m outpu t po wer can b e re duc ed to min i mal. in orde r to prev ent the cu r r e n t l i m i t fr om di st or tio n s ca use d b y le ading e dge sp ikes , a lea ding edg e vcc 1 pw m - l a t c h ga t e driver gate t 5v c a . t = 1 3 0 n s c1 1 cur r e nt li m i t i n g c10 1. 6 6 v c12 & 0.2 5 v leadi ng ed g e b l ank i ng 2 20n s g1 0 sp i k e bl a n k i n g 19 0 ns o v er power protection v cs t h acti v e bu r s t mo d e pw m l a t c h ff 1 10k d1 1pf pw m - o p cs la t c h ed o f f mo d e opp
f3 pwm controller ice3bs03ljg functional description version 2.0 1 3 6 dec 200 7 bla n king is in te grated in the c u rrent s ens e p a th for the c o mpa r a t o r s c 10, c12 an d th e pwm-op. t he o u tput o f comp arator c1 2 is activa te d by the and ga te g1 0 if ac tiv e burst mod e is entered . whe n it is a c tiv a ted, the c u rre n t lim i ting is red u ce d to 0.25v. t h is volt age level determi n es th e ma ximum p o we r le vel in acti ve burst mode. f u rth e rmore, the comp arator c 11 is imple m ented to d e te ct d ang erous c u rre n t lev e ls whic h c o u l d oc cu r if there is a sho r t wind in g in the tra n s f orme r or the s e co nda ry diod e is sh orte n. to ens ure tha t th ere is no a ccid entally en te ring of th e latc hed m ode b y the c o mpa r a t o r c11 , a 190 ns sp ik e blank ing time is integ r a t e d in the o u tput p a th of c o mp arator c1 1. 3 . 6.1 l e a ding e dge blan king f i g u re 18 lea ding ed ge blan king wh enev er the po wer mosf e t is s w itc h e d on, a lea d ing edg e s p ike is g ene ra te d d ue to th e p r ima r y - s i d e cap a citanc es an d rev e rse rec o ve ry time of the s e co nda ry -s ide rec t ifie r. this s p ike c an c aus e th e gate d r ive to sw itc h off unin t e n tio nally. in orde r to avo i d a p r e m ature te rm in atio n of the swi t ching pulse, this spike is bla n ke d out w i th a time con s tant of t le b = 220 ns . 3. 6.2 p ropaga tion dela y compe n sation f i g u re 19 current limiting in c a se of ov ercurrent d e tection, there is alway s p r o paga tio n d e lay to switch off the ex ternal p o we r mosfet. an overshoot of the peak current i peak is indu ced to the d e lay, which de pen ds on the ra tio of d i / dt o f the pe ak cu rren t (se e figure 19 ). the ov ersh oot of s i g nal2 is large r th an o f signa l1 du e to the s t eepe r rising wa veform. this c han ge in th e slop e is d epending on th e ac in put v o ltage. propa gation delay c o mpe n sa tion is integrated to re duc e the ov ersho o t du e to d i /dt o f the ris i ng prima r y cu rren t. thu s th e propa gation de la y time b e twee n ex ceed ing the current se nse th re shol d v cst h and th e switch in g off o f the e x ternal po wer mosfe t is co mpen sated ove r temp erature with in a wide ran ge. current limiting is the n very ac cu ra te . for exa m ple, i pe ak = 0. 5a wit h r s ens e = 2 . th e current se nse th re sh old is set to a static v o ltage leve l v cs th =1 v with out p r o pag atio n de lay comp ens atio n. a current ra mp o f di/dt = 0 . 4a /s , or dv se nse /dt = 0.8v /s , and a propagation d e lay time of t prop ag ati on del a y =18 0ns leads to an i pe ak o v ers hoo t o f 1 4 .4%. with the p r o pag atio n dela y com pen sation, th e ove r s h o o t is on ly aroun d 2% (s ee f i g u re 20). figu re 2 0 o v ercu rren t sh utdown figu re 2 1 d y na mic voltage t h resh old v cst h t v sense v cs t h t leb = 220ns t i sense i lim i t t pr opagation dela y i o v er s hoot 1 i peak 1 s i gnal 1 signal 2 i ov er s hoot 2 i peak 2 0,9 0,95 1 1, 05 1, 1 1, 15 1, 2 1, 25 1, 3 0 0 ,2 0 ,4 0 ,6 0 ,8 1 1 , 2 1 ,4 1 ,6 1 ,8 2 with compensa ti o n without compensation dt dv sense s v p se ns e v v t v cs t h v os c signal 1 s i gnal 2 v se nse propagati o n d el ay max. duty cycl e off time t
f3 pwm controller ice3bs03ljg functional description version 2.0 1 4 6 dec 200 7 t he pro pag atio n d e lay com pens ation is rea l iz ed by me ans of a d y na mic th re sho l d v o lta ge v cs t h (se e figure 2 1 ). in c a s e of a s t e epe r slop e th e switch off o f the dr iv er is e a r lie r t o co m p en s a t e th e de la y. 3.7 c ontrol unit t he co ntro l un it c ontains the fu nctions fo r a c tiv e bu rs t mo de, auto re start mo de a nd la tc hed off mod e . t h e acti ve burst mode and th e a u to r e st ar t m o de b o t h ha v e 20 m s in te rn al bl an k i ng t i m e . f o r t h e a u to re start mode , a furth e r exten dab le blank ing t i me is a c hiev ed by add in g ex ternal c apa cito r at bl p i n. by me ans of this blan king time , th e ic avo i d s entering into th ese two mod e s ac cide ntally . fu rthe rm ore tho s e b u ffer time for the ov erlo ad detec tion is v e ry use f u l fo r the app lic a tio n tha t w o rks in low cu rren t b u t requ ires a s hort d u ratio n of h i g h current occ a s i o nally. 3 . 7.1 b a s ic a nd ex te nda ble blanking m ode f i g u re 22 bas i c and ex tend able blan king mo de t here a r e 2 k i nds of blan king mode ; bas ic mo de a n d the e x tend able mo de. th e bas ic mod e has an interna l p r e - s e t 20ms blan king time w h ile the ex tend able mo de h a s e x tend ed bla n king time to b a sic mode by c onn ecting an externa l ca pac itor to th e bl pin. f o r the e x tend able m ode , the gate g5 is b l ock ed eve n thou gh the 20 ms blank in g time is rea c h ed if a n externa l c apa ci to r c bk is ad ded to bl pin. while th e 20 ms blan king time is pas se d, th e s w itc h s1 is op ene d by g2. the n the 0.9v clamp ed vo lta ge at bl p i n is ch arged to 4.0v throug h the interna l i bk c o n s tant cu rren t. t hen g5 is ena bled by c o mpa r a t o r c3. a f ter th e 3 0us sp ike blank ing time, the auto res t a r t mo de is ac ti va te d. for ex ample, if c bk = 0. 22 u f , i bk = 13 ua blank ing tim e = 20 ms + c bk x (4.0 - 0. 9) / i bk = 72ms t h e 2 0 m s bl an k i ng tim e ci rcu i t af te r c4 is dis a bl ed b y th e so ft stat bloc k s u ch tha t the con t roller can start u p prope rly . the active burst mod e ha s ba sic b l ank in g mod e on ly while th e a u to re start mod e h a s bo th the bas ic a nd th e ex te ndab le blank ing mod e . 3.7.2 a ctiv e burst mode the ic enters ac tiv e b u rst mo de und er low loa d conditi ons. wi th the active bu rs t mod e , t he ef fi c i e n cy increa ses sign ifica n tly at lig h t lo ad c ond ition s wh ile s t ill maintainin g a low ripple on v out a nd a fas t res pon se o n load jum p s. during a c tiv e bu rs t mo de, th e ic is co ntro lled by the fb s i gnal. sinc e the ic is a l w a ys ac tive , it can be a very fa st res pon se to the quick ch ange at the fb sig nal. th e start up ce ll is k ept of f in order to minimiz e the p o we r los s . fi gu re 2 3 a c t i ve bur s t mod e the act i ve burst mode i s locat e d in the cont rol unit . figu re 2 3 s h o w s the related co mpon ents. c3 4.0v c4 4.0v c5 1.23v & g5 & g6 0.9v s1 1 g2 control unit active burst mode auto restart mode 5.0v fb c bk 20ms blanking time 20ms blanking time spike blanking 3 0us # i bk soft start block bl c4 4. 0v c6 a 3. 5v c5 1. 23v fb cont r ol uni t act i v e bu r s t m ode i nt er nal b i as & g10 c ur r ent li m i t i ng & g6 c6b 3.0v & g1 1 20 ms b l anki ng ti m e
f3 pwm controller ice3bs03ljg functional description version 2.0 1 5 6 dec 200 7 3 . 7.2.1 e n t e r ing ac tive b u rs t mo de t he f b s i gnal is k ept mo nito ring by the com parator c4 . du rin g no rm al ope ra tio n , th e interna l blank ing time c oun te r is res e t to 0. whe n fb signa l falls b e low 1.23v , it s t a r ts to c oun t. wh en the cou n ter reac h 20ms a nd fb s i g nal is still below 1.23 v, th e s y s t e m en te rs the a c tive bu rs t mo de. t h is tim e w i ndow p r e v en ts a s udd en e n te rin g into the ac tive burs t m ode due to large lo ad jumps. after enteri ng active burst mo de, a bur s t fl ag i s set and the internal b i a s is s w itc hed off in o r d e r to red u ce the c u rre n t c ons ump t ion o f the ic to ap prox. 450 ua. it n eed s th e ap plic ation to enforc e th e vcc v o lta g e a bov e the un dervo lta ge loc kou t leve l of 10.5v su ch that th e s t a r tup ce ll will not be switch ed on a ccid entally. or oth e rwise t he pow er los s will increa se d r a s tic a lly. t he minimum vcc le ve l during active bu rs t mo de dep end s on th e lo ad co nditio n and the a pplication . the lowes t vcc leve l is rea c he d a t no lo ad c ond ition. 3 . 7.2.2 w orking in ac tive bu rs t mod e after entering the active b u rst mode , the fb v o lta g e rises as v ou t starts to dec re as e, w h ich is d ue to the ina c tive pwm s e c t ion . the co mparator c 6a monitors the f b sign al. if th e vo ltag e le ve l is la rg er tha n 3.5v , the interna l circu i t will be ac tiv a ted; the interna l bias c i rc uit res u mes a nd starts to provid e s w itc h ing pu lse. in ac tiv e bu rs t mode the g a te g10 is relea s e d an d the c u rre n t lim i t is reduc ed to 0.25 v. in on e h and , it c a n red u ce th e c ond uc tion loss an d the other h and , it c a n red u ce the aud ible n o ise . if th e loa d at v out is stil l kept u n ch ang ed, the f b sign al w i ll drop to 3 . 0 v . at th is le ve l the c6b dea ctivates the in te rn al circu i t a gain by sw it ch in g o f f t h e in te rn a l bi as . t h e ga t e g 1 1 is ac tiv e a gain as the bu rs t flag is set after entering ac tiv e bu rs t mo de. in active burst m ode , th e f b v o lta ge is c han ging like a s a w too t h betwe en 3 . 0 v an d 3.5v (s ee figure 24 ). 3 . 7.2.3 l e aving ac tiv e burst mo de the fb vol t age will increase i m mediately if ther e i s a h i g h loa d jum p . this is obs erved by the com parator c4 . as the c u rre n t limit is ap p. 25% d u rin g ac tiv e bu rs t mo de, a certain load jump is n eed ed so tha t the fb si gn a l c a n e x c e ed 4. 0v . a t th a t tim e t h e co m p ar at or c 4 r e s e t s t h e ac ti ve bu rst mode co nt ro l whi ch i n t u r n bl oc ks th e co m p ar at or c 1 2 by t h e ga te g1 0 . th e maximum cur r ent can t h en be resumed to stabilize v out. figu re 2 4 s i g nals in ac tiv e burst mode 1.23v 3.5v 4. 0v v fb t t 0. 25v 1. 06v v cs 10. 5v v vcc t t 450ua i vcc t 2. 5m a v ou t t 20m s b l anki n g t i m e c u r r ent limit level during active burst mode 3.0v ente r i n g ac t i v e bu r s t m ode leavi n g ac tive burst mode blanking ti m e r
version 2.0 16 6 dec 2007 f3 pwm contr o lle r ice3bs03ljg functional description 3 . 7.3 p rotection mo des t he ic prov id es sev e ral p r o t e c tion fe atu r e s which are s epa ra te d into tw o c a tego ries . som e e n ter la tc hed off mo de and th e o t h e rs e n ter au to res t art m ode . besid e s the pre-de fine d protection feature for the la tc h off mo de, there is a l s o an externa l latch off en able p i n fo r c u stom er define d l a tc h of f protection fe atures. t h e l a tc he d off mo de can on ly b e res e t if vcc falls b e low 6 . 23 v. bo th m odes preve n t the smp s from de stru ctive s t a t e s .the following tab l e s hows the relations hip b e tw een p o ss ible sy stem fa ilu r e s and the c hos en pr ot e c ti on m o d e s . 3. 7 . 3 . 1 l at ch e d o ff m o d e f i g u re 25 latc hed off mo de the vcc vo ltag e is obs erve d b y c o mpa r a t o r c1. if th e vcc vo lta ge is > 25.5v , th e ove r v oltage de te ction is ac tiva te d. it e n ters th e la tc h off mo de. the internal vo ltag e re fe re nce is sw itc hed off mo st of th e tim e onc e la tc hed off mod e is en te re d in order to minimize the cu rren t co ns u m ption of the ic. th is latc hed off mod e c an only be res e t if the v vcc < 6. 23 v . in this m ode, o n ly the uvl o is w o rking which co ntro ls th e startu p cell by s w itching on/off a t v vc con /v vcco ff . during this p has e, th e ave r a ge c u rre n t con s ump t io n is only 25 0 a. as there is n o lon ger a se lf-sup ply by th e aux ilia ry wind in g, the vcc drops . the und e rvo l tag e loc ko ut s w itche s on the integ r a t e d startu p cell whe n vcc fa lls be lo w 1 0 .5v. th e startup cell is switche d o f f aga in w hen vcc ha s exc eed ed 18 v. onc e the l atche d off mo de w a s e n tered, there is no start up p has e whe nev er the vcc ex cee d s the switch -o n lev e l o f th e und e rvoltage lo cko ut. t herefore th e vcc vo ltag e ch ange s b etwee n the switch -o n an d s w itc h-off le ve ls of th e u nde rv oltage loc ko ut with a s a w too t h s hape (se e fi gu re 2 6 ) . figu re 2 6 s i g nals in la tc hed off m ode the th ermal sh utdown bloc k monitors the junc tio n te mpe r a t ure of the ic. a f ter de te cting a junc tio n te mper a t ure high er than la tc hed ther ma l sh utdow n t e m p er at u r e ; t js d , the la tc hed off m ode is en te re d. t h e s i g n a ls c o m i ng fr om th e te mperature de te ction an d vcc ove r v o ltage detec tio n are fed into a spik e blan king with a time co nstan t of 30 s in order to ens ure t h e system reli abili ty. furthermo re , a s hort windin g or sho r t dio de on th e se con dary sid e c an be d e tected by the c o mp arator c1 1 whic h is in parallel to the prop agation delay co mpen sated c u rre n t lim i t c o mp arator c1 0. in n o rmal ope ra ting mod e , comp arator c10 con t rols th e max i m u m lev e l of the cs sig nal at 1.06v . if the r e is a vc c overvolta g e l atche d off mod e ov erte mperature l atched off mod e sh ort windin g /short d i o d e l atche d off mod e bl p i n < 0.25v l a tche d off mod e ov erload a u to res t art m ode op en lo op a u to res t art m ode vc c unde rv oltage a u to rest art m ode sh ort optoc oup ler a uto res t art m ode c1 25 .5v sp ike blanking 3 0us & g1 1 g3 t h er m a l s hu t do w n t j >1 30 c lat c hed of f m o d e vcc c11 1.6 6v sp i k e b l an k i ng 19 0 n s cs v o l t ag e re f e r e n c e cont r o l u n it latc h e d o f f mo d e r e s e t v vc c < 6 . 23v t le bl c2 la t c h en a b l e si g n a l 30 u s b l ank i ng ti m e 0.25 v 1ms co u n t e r uvlo # 10. 5v t i vccstar t t 0. 9m a v ou t v vc c 18 v
f3 pwm controller ice3bs03ljg functional description version 2.0 1 7 6 dec 200 7 failure suc h as s hort w i n d ing or sh ort diod e, c 10 is no lon ger able to limit the cs s i g nal at 1 . 0 6 v. ins t ead the c o mpa r a t o r c1 1 de te cts the pe ak c u rre n t voltage > 1 . 66 v and e n ters th e latch ed off mod e im mediately in o r d e r to ke ep th e smps in a sa fe s t a ge. in c a se th e p r e - d e fin ed l a tch o f f features are no t s u ffic ie nt, th ere is a cu stom er defined ex te rn al l a tch en able fea t u r e . th e latch off mod e can be trigg e red by pu ll ing do w n t h e bl pi n to < 0. 25 v . it c a n si mp ly ad d a trigge r s i gna l to the bas e o f the externa l ly add ed transi s tor, t le at th e bl pin . to ens ure th is latch func tio n w i ll no t be mis-trigge re d d u rin g s t a r t u p , a 1 m s d e lay time is impleme n te d to blank the uns ta ble sign al. 3 . 7.3.2 a u t o r estart mo de f i g u re 27 auto re start mod e in c a se of ov erlo ad o r open loo p, th e fb ex cee d s 4. 0v which will be observed by compar at or c4. then the in te rn al blank ing c oun te r s t a r ts to c oun t. whe n it rea c he s 2 0 ms , th e s w itc h s 1 is releas ed. t hen the c l a m pe d v o ltage 0.9v at v bl ca n in crea se. when there is no externa l c apa cito r c bk c onn ec te d, the v bl will rea c h 4.0v imme diately. wh en both the inpu t sign als a t an d ga te g5 is p o sitive, the auto-res tart mode will be a c tiv a ted afte r th e ex tra sp ik e b l a n kin g time o f 3 0us is e l a p se d. ho wev e r, whe n an extra blank ing time is n eede d, it c an be ach i eve d by add in g an externa l c apa ci to r, c bk . a c ons ta nt current so urce o f i bk will start to cha r g e th e c apa citor c bk fr om 0. 9v to 4.0v after the s w itc h s1 is rele ase d . the ch arging time from 0.9v to 4 . 0v a r e the ex tenda ble blan king tim e . if c bk is 0.22 uf a nd i bk is 1 3ua, th e exten dab le b l ank in g time is arou nd 5 2 ms and the total blank ing time is 72 ms. in com b ining the fb a nd blank in g time, there is a b l a n k i n g wind ow gen erated whic h p r e v e n ts the s y s t e m to enter a u to res t a r t mod e d ue to large load jump s. in ca se of vcc u nde rv oltage, the ic enters in to th e auto res t art mod e and s t a r ts a ne w startu p cy cle. sho r t optoc oup ler a l so lea d s to v cc un dervo lta ge as th ere is no se lf sup p ly after ac tiv a ting the internal re fe re nc e a nd bia s . in con t ras t to the l a tche d off mo de, there is a l w a ys a startu p ph as e with switchin g c ycle s in auto res t a r t mod e . after this start u p p has e, the c ond ition s are aga in ch eck ed w hethe r the fa ilure m ode is still p r e s en t. normal operation is resumed once the failure mode is removed that had caused the auto restart mode. c3 4.0v c4 4.0v & g5 0.9v s1 1 g2 control unit auto restart mode 5.0v bl fb c bk 20ms blanking time spike blanking 30 us # i bk
version 2.0 18 6 dec 2007 f3 pwm contr o lle r ice3bs03ljg electrical charact erist i cs 4 e lectrical characteristics no te : a ll vo ltag es are meas ured with res pec t to g r o und (p in 8). the v o lta ge le ve ls a r e va lid if othe r ra ting s are not violated . 4.1 a bsolute maximum ratings no te : a bs olute maximu m ratings a r e d e fin ed as ratings , wh ic h whe n b eing ex ce ede d m ay lead to des truc tio n of th e integrated circuit. f o r th e s a me rea s on mak e su re , tha t a n y cap a citor that will b e c onne cted to pin 7 ( v c c ) i s di sc ha rg e d be fo re a s se m b l i n g th e ap p lic at io n cir c u i t . 4.2 operating range no te : w ithin the op erati ng range the ic op erate s as d e sc rib ed in th e fu nctiona l d e sc rip t ion . par a meter s ymbol l imi t values uni t remarks min. max. hv vo lta g e v hv -5 0 0 v vc c supp ly voltage v vcc -0.3 27 v fb vo lt ag e v fb -0.3 5. 0 v cs vo lta g e v cs -0.3 5. 0 v j unc tion t e mp erature t j -40 1 50 q c storag e temp erature t s -55 1 50 q c t hermal res i stanc e j unc tion -amb ient r th ja -1 8 5 k / w es d capa bility (incl. d r a i n p i n ) v esd - 2 kv h u man b ody mode l 1) 1) according to eia/jes d 22-a1 14-b (d isch ar ging a 10 0pf c apa citor throu gh a 1.5k : se rie s re sistor) parameter s ymbol limit values unit remarks min. max. vc c supp ly voltage v vcc v vccoff 26 v j unc tion t e mp erature o f co ntro ller t jco n -25 1 3 0 c ma x valu e limited du e to therma l sh u t do w n of c o n t r o l l er
f3 pwm controller ice3bs03ljg electrical characteristics version 2.0 1 9 6 dec 200 7 4.3 c haracteristics 4 . 3.1 s u pply sec t ion no te : t he e l e c tric al c harac te ris t ic s in volv e th e s p rea d o f va lu es within th e spe c ifie d sup p ly vo ltag e and junc tio n te mperature rang e t j fr om ? 2 5 q c to 1 2 5 q c . ty pica l v a lue s re pres ent th e media n valu es, whic h are re la te d to 2 5 c. if n o t othe rw is e stated , a su pply v o lta ge of v cc = 1 8 v is as su med. 4.3.2 internal voltage reference pa ra meter s ymb o l l imit va lues unit test condit ion min. typ. max. start u p current i v ccs t a rt - 1 50 25 0 p a v vcc =16.5v vc c charge c u rre n t i v ccc h a rg e1 -- 5 . 0 m a v vcc = 0v i v ccc h a rg e2 0.55 0.90 1 . 6 0 ma v vcc = 1v i v ccc h a rg e3 -0 . 7 -m a v vcc =16.5v l eak age cu rren t of start up cell i s t art lea k -0 . 2 5 0 p a v hv = 4 50v, v vcc =1 8v su pply cu rren t with inacti ve gate i v ccs u p 1 -1 . 5 2 . 5 m a su ppl y cu rr en t wi t h act i ve ga te i v ccs u p 2 -2 . 5 4 . 2 m a i fb = 0a, c loa d =1nf su pply cu rren t in latc hed off mo de i v ccla t c h -2 5 0 - p a i fb = 0a su pply cu rren t in au to re start mo de with in active ga te i v ccrestar t -2 5 0 - p a i fb = 0a su ppl y cu rr en t i n ac ti ve b u r s t mo de with in active ga te i v ccbu r s t 1 - 4 50 95 0 p a v fb = 2.5v i v ccbu r s t 2 - 4 50 95 0 p a v vcc = 11.5v, v fb = 2.5v vcc turn-on thr e shol d vcc turn-off thr e shol d vc c turn-on/off hy steres is v vcco n v vcco ff v vcch y s 17.0 9.8 - 18 .0 10 .5 7.5 19 .0 11 .2 - v v v pa ra meter s y m bol l i mit va lu es u n it tes t co nditio n min. ty p. max . t r imme d referenc e voltage v ref 4 . 90 5.00 5.10 v m ea sured a t pin f b i fb = 0
version 2.0 20 6 dec 2007 f3 pwm controller ice3bs03ljg electrical characteristics 4 . 3.3 p wm se ctio n 4.3.4 soft start time pa ra meter s y m bol l i mit va lu es u n it tes t co nditio n min. ty p. max . f i x ed oscilla t o r freq uen cy f osc1 5 6 .5 65 73 .7 k h z f osc2 59 . 8 6 5 . 0 7 0. 2 k h z t j = 25 c f r e quen cy j i ttering ra nge f ji tter - 2 . 6 -k h z t j = 25 c max. duty cycle d ma x 0 . 70 0.75 0.80 min. duty cycle d mi n 0- - v fb < 0. 3v pwm- op ga in a v 3. 0 3 .2 3 . 4 vo ltag e ramp o f fse t v offset-ramp -0 . 6 - v v fb operating ra nge min le vel v fb m i n -0 . 5 -v v fb operating ra nge ma x le ve l v fb m a x - - 4 . 3 v c s =1 v , li m i te d by comp arator c 4 1) fb pu ll- u p re s i st or r fb 9 15.4 2 2 k : 1) the p a rame ter is not sub j ected to produ ction test - ver i fied by de sig n /cha ra cterization pa ra meter s y m bol l i mit va lu es u n it tes t co nditio n min. ty p. max . so ft start time t ss -20-ms
f3 pwm controller ice3bs03ljg electrical characteristics version 2.0 2 1 6 dec 200 7 4. 3.5 c ontr ol unit note: the trend of all the voltage levels in the cont rol unit is the same regarding the deviation except v vccovp and v vccpd pa ra meter s y m bol l i mit va lu es un it te st co nditio n min. typ. max. cla m ped v bl voltag e d u ring no rm al op erating mod e v bl cl mp 0 . 8 5 0.90 0.9 5 v v fb = 4v bla n king time vo ltag e limit for c o m p ar at o r c3 v bkc3 3 . 8 5 4.00 4.1 5 v ov er lo ad & ope n l oop detec t ion l i mit fo r com parator c 4 v fb c 4 3 . 8 5 4.00 4.1 5 v acti ve burst mode level for c o m p ar at o r c5 v fb c 5 1 . 1 2 1.23 1.3 4 v acti ve burst mode level for c o m p ar at o r c6 a v fb c 6 a 3. 35 3 . 5 0 3 . 65 v a ft er a c t i ve b u rs t mod e is entered acti ve burst mode level for c o m p ar at o r c6 b v fb c 6 b 2. 88 3 . 0 0 3 . 12 v a ft er a c t i ve b u rs t mod e is entered ov ervo ltag e detec t ion l i mit v vccovp 2 4 .5 25 .5 26.5 v l a tc h ena b le leve l at bl pin v le 0. 17 0 . 2 5 0 . 33 v > 30 i bk 9. 1 1 3. 0 1 6 . 9 t jsd 130 1 40 1 5 0 c bu i l t - in b l a n ki n g ti me fo r ov erload protec tio n o r en te r acti ve burst mode t bk - 2 0 - ms withou t ex te rn al ca pac itor at b l pin inhibi t time for latch enable func tio n durin g st art up t ihle - 1 .0 - m s a ft er ic t u r n s on sp ike blank in g time b e fore latch off or auto restar t prote ction t spi k e -3 0 - v vccp d 5 . 2 6 .23 7 .8 v a fte r l a tche d off mo de is entered
version 2.0 22 6 dec 2007 f3 pwm contr o lle r ice3bs03ljg electrical charact erist i cs 4 . 3.6 c u r r e nt limiting 4.3.7 driver section pa ra meter s y m bol limit value s unit t est cond ition min. typ. max. pe ak cu rren t limitatio n (incl. pro pag atio n delay ) v cs th 0.99 1.06 1 . 1 3 v d v se ns e / d t = 0.6v/ s (se e figure 20 ) pe ak cu rren t limitatio n during acti ve burst mode v cs2 0.21 0.25 0 . 3 1 v l eadin g edge b l a n kin g t leb -2 2 0 - n s cs input bias current i csbi as -1 .5 - 0 . 2 - a v cs =0v ov er c u rre n t d e te ction for l a tc he d off mode v cs1 1.57 1.66 1 . 7 6 v cs sp ike blan king for c o m p ar at o r c1 1 t css p ike -1 9 0 - n s par a meter s ymbol l imit val u es uni t test condit ion min. typ. max. ga te low vo lta g e v gatelo w -- 1 . 2 v v vcc = 5 v i ga te = 1 ma -- 1 . 5 v v vcc = 5 v i ga te = 5 ma -0 . 8 -v i ga te = 0 a -1 . 6 2 . 0 v i ga te = 20 ma -0.2 0. 2 - v i ga te = -20 ma ga te high vo ltag e v ga t e hi gh -1 0 . 0 - v v vcc = 26 v c l = 6 80p f -9 . 0 -v v vcc = 15 v c l = 6 80p f -8 . 0 -v v vcc = v vcco ff + 0.2v c l = 6 80p f ga te rise time (incl. gate rising slop e) t ri se -1 5 0 -n s v ga te = 2v .. .9v 1) c l = 6 80p f 1) transient reference value gate fall time t fa ll -5 5 - n s v ga te = 9v .. .2v 1) c l = 6 80p f gate current, peak, r i si ng e d ge i gate -0.17 - - a c l = 6 80p f 2) 2) the parameter is not subjected to production test - verified by de sign/characterization gate current, peak, f a llin g edge i gate - - 0.39 a c l = 6 80p f 2)
f3 pwm controller ice3bs03ljg outline dimension version 2.0 2 3 6 dec 200 7 5 o utline dimension figure 28 pg-dso-8 (pb-free plat ing plastic dual small outline) dimensions in mm pg-dso-8 (plastic dual small outline)
version 2.0 24 6 dec 2007 f3 pwm contr o lle r ice3bs03ljg marking 6m a r k i n g figure 29 marking for ice3bs03ljg marking
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